An ingenious approach for the layout-design of VLSI-chips has been presented. It is contrary to the classical, serial process, where first the cells are placed and global routes for the nets are determined, before the detailed routing is done. There, global routing and floorplanning is done with having a global view on the developing layout. In the described algorithm, the detailed routing is done during the composition of partial layouts which are joint to a complete solution during the construction of the genotype, a binary slicing tree. In this approach, the global view remains to the genetic algorithm, which optimizes the general placement and the global routes on the layout surface.