In the floorplanning phase, the macro cells have to be positioned on the layout surface in such a manner
that no blocks overlap and that there is enough space left to complete the interconnections.
The input for the floorplanning is a set of modules, a list of terminals (pins for interconnections)
for each module and a netlist, which describes the terminals which have to be connected.
At this stage, good estimates for the area of the single macro cells are
available, but their exact dimensions can still vary in a wide range.
Consider for example a register file module consisting of 64 registers.
It can be organized as a 
, 
, 
or 
array
which yields four implementations with different aspect ratios.
These alternatives are described by shape-functions [7].
A shape-function is a list of feasible height-/width-combinations for the layout of a
single macro cell (cf. fig. 2).
The result of the floorplanning phase is the sized floorplan, which describes the position of the
cells in the layout and the chosen implementations for the flexible cells.
Figure 2: The shape-function for a macro cell with three different implementations
There exist many different approaches to the floorplanning problem. Wimer et al. [10] describe a branch and bound approach for the floorplan sizing problem, i.e. finding an optimal combination of all possible layout-alternatives for all modules after placement. While their algorithm is able to find the best solution for this problem, it is very time consuming, especially for real problem instances. Cohoon et al. [2] implemented a genetic algorithm for the whole floorplanning problem. Their algorithm makes use of estimates for the required routing space to ensure completion of the interconnections. Another more often used heuristic solution method for placement is Simulated Annealing [8,11].